Due to structural simplicity, DRAMs (dynamic random access memories) can provide more memory cells per unit chip area than other types of memories such as static random access memories. A DRAM is constituted by a plurality of DRAM cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line is asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor to be read by a sense amplifier through a bit line. During a write operation, the data to be written is provided on the bit line while the word line is asserted.
To satisfy the demand for greater memory storage, DRAM memory cells need size reduction. DRAM memory cell size can be reduced in several ways. One way is to reduce the minimum feature size of a DRAM memory cell through the advances in process technology. Another way to reduce the size of a DRAM memory cell is by designing a memory cell having a smaller feature size. For example, many DRAM chips on the market today have a memory cell size of 4F2, where F stands for the photolithographic minimum feature width or critical dimension (CD).
FIG. 1 and FIG. 2 illustrate a method for preparing a dynamic random access memory structure 10 according to prior art. First, fabrication processes are performed to form a substrate 19, and a dielectric structure 21 overlaying the substrate 19 is then formed by the deposition process. In particular, the substrate 19 includes a semiconductor substrate 11 with a shallow trench isolation 13, recessed gates 15, and doped regions 17 in the semiconductor substrate 11. Subsequently, fabrication process is performed to form conductive lines 31 serving as word lines on the recess gates 15, and spacer structures 33 on the sidewall of the conductive lines 31.
The forming of the dielectric structure 21 includes the steps of forming a first insulation layer 23 such as an oxide layer overlaying the substrate 19, forming a bit-line contact plug 27 in the first insulation layer 23 and connected to one of the doped regions 17, forming a second insulation layer 25 such as a boro-phospho-silicate glass (BPSG) layer overlaying the first insulation layer 16, and forming a bit line 29 in the second insulation layer 25 and connected to the bit-line contact plug 27. The bit-line contact plug 27 and the bit line 29 are shown as a dashed line to emphasize that the bit-line contact plug 27 and the bit line 29 are buried in the dielectric structure 21. Subsequently, a capacitor contact plug 35 is formed in the dielectric structure 21 and connects to one of the doped regions 17, as shown in FIG. 2.
However, the bit-line contact plug 27 and capacitor contact plug 35 both are cone-shaped, and the contact area between the doped regions 17 and the bit-line contact plug 27 (and capacitor contact plug 35) is the minimum, and the contact resistance increases as the contact area decrease. In other words, the bit-line contact plug 27 and capacitor contact plug 35 fabricated by the conventional technical can not meet the demand for greater memory storage of DRAM due to the higher contact resistance.